[Xen-devel][PATCH]Fix the read error from IRR,ISR and TMR

["Xin, Xiaohui" <xiaohui.xin@xxxxxxxxx>]

This patch fixes the error when read from APIC registers like IRR, ISR and TMR, guest cannot get correct value.

Since from SDM3 spec, for APIC registers, all 32-bit registers should be accessed using 128-bit aligned 32bit loads or stores.

And wider registers (64-bit or 256-bit) must be accessed using multiple 32-bit loads or stores.

 

In old APIC virtualization code, we use IRR, ISR and TMR which are 256-bit registers as contiguous bit maps other than multiple 32-bit.

So guest always fetch error values.

 

Signed-off-by: Xiaohui Xin <xiaohui.xin@xxxxxxxxx>

Signed-off-by: Yunhong Jiang <yunhong.jiang@xxxxxxxxx>

Signed-off-by: Eddie Dong <eddie.dong@xxxxxxxxx>

apic_1.diff
Description: apic_1.diff

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