Re: [Xen-devel] Essay on an important Xen decision (long)

[Mark Williamson <mark.williamson@xxxxxxxxxxxx>]

> Is VP on x86 expensive in terms of performance or complexity?

One nasty thing for VP on x86 is the compulsory hardware PT walker - IA64 
allows the hypervisor to handle TLB fills on behalf of a guest, so that it 
can perform phys-to-machine translation.  IA64 has a hardware PT walker but 
you aren't *forced* to use it.

IIRC, PPC also performs P-to-M translations in the hypervisor, but I vaguely 
recall that happening during an explicit pagetable update hypercall - kind of 
a middle road between the x86 and IA64 approaches...  Some PPC guy may jump 
in and correct me at this point, though ;-)

> I imagine that you would have to always have shadow paging enable but
> you could still do bulk updates ala writable page tables so the
> performance cost should be minimal I would think.
>
> Trying to understand the memory system in more details so any additional
> info is much appreciate :-)

I don't see why that couldn't perform decently, although it'd have more 
overhead than allowing the guest to manage its pagetables directly...  I 
*thought* this was intended to be supported at some point, but I'm not sure 
if it's been needed yet.  Others may have more concrete numbers for the 
performance - I think writable PTs got benchmarked against shadowing at some 
point.

Cheers,
Mark

> Thanks,
>
> Anthony Liguori
>
> > If ia64 does decide to back off from the P==M route then I suspect VP
> > is the way to go (which is I think how ia64 domU's currently work
> > anyway).
> >
> >  -- Keir
>
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> Just a question. What use is a unicyle with no seat?  And no pedals!
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