[Xen-changelog] [xen-unstable] [HVM] Yet another MCA/MCE MSR.

[Xen patchbot-unstable <patchbot-unstable@xxxxxxxxxxxxxxxxxxx>]

# HG changeset patch
# User Tim Deegan <Tim.Deegan@xxxxxxxxxxxxx>
# Date 1186139435 -3600
# Node ID 52e5c110aadb31d6086f0785dc1f52160bc8e5ba
# Parent  a451b0ab40d9679d9b81b868f909f9e459961fec
[HVM] Yet another MCA/MCE MSR.
Signed-off-by: Tim Deegan <Tim.Deegan@xxxxxxxxxxxxx>
---
 xen/arch/x86/hvm/svm/svm.c |    1 +
 xen/arch/x86/hvm/vmx/vmx.c |    1 +
 xen/include/asm-x86/msr.h  |    5 +++++
 3 files changed, 7 insertions(+)

diff -r a451b0ab40d9 -r 52e5c110aadb xen/arch/x86/hvm/svm/svm.c
--- a/xen/arch/x86/hvm/svm/svm.c        Fri Aug 03 09:04:29 2007 +0100
+++ b/xen/arch/x86/hvm/svm/svm.c        Fri Aug 03 12:10:35 2007 +0100
@@ -2159,6 +2159,7 @@ static void svm_do_msr_access(
         case MSR_K8_MC2_STATUS:
         case MSR_K8_MC3_STATUS:
         case MSR_K8_MC4_STATUS:
+        case MSR_K8_MC5_STATUS:
             /* No point in letting the guest see real MCEs */
             msr_content = 0;
             break;
diff -r a451b0ab40d9 -r 52e5c110aadb xen/arch/x86/hvm/vmx/vmx.c
--- a/xen/arch/x86/hvm/vmx/vmx.c        Fri Aug 03 09:04:29 2007 +0100
+++ b/xen/arch/x86/hvm/vmx/vmx.c        Fri Aug 03 12:10:35 2007 +0100
@@ -2596,6 +2596,7 @@ static int vmx_do_msr_read(struct cpu_us
     case MSR_K8_MC2_STATUS:
     case MSR_K8_MC3_STATUS:
     case MSR_K8_MC4_STATUS:
+    case MSR_K8_MC5_STATUS:
         /* No point in letting the guest see real MCEs */
         msr_content = 0;
         break;
diff -r a451b0ab40d9 -r 52e5c110aadb xen/include/asm-x86/msr.h
--- a/xen/include/asm-x86/msr.h Fri Aug 03 09:04:29 2007 +0100
+++ b/xen/include/asm-x86/msr.h Fri Aug 03 12:10:35 2007 +0100
@@ -239,6 +239,11 @@ static inline void write_efer(__u64 val)
 #define MSR_K8_MC4_STATUS              0x411
 #define MSR_K8_MC4_ADDR                        0x412
 #define MSR_K8_MC4_MISC                        0x413
+
+#define MSR_K8_MC5_CTL                 0x414
+#define MSR_K8_MC5_STATUS              0x415
+#define MSR_K8_MC5_ADDR                        0x416
+#define MSR_K8_MC5_MISC                        0x417
 
 /* Pentium IV performance counter MSRs */
 #define MSR_P4_BPU_PERFCTR0            0x300

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